1. Field of the Invention
The present invention relates to a method for forming an isolation layer of a semiconductor device, and more particularly to a method for forming an isolation layer of a semiconductor device capable of forming a field oxide layer having a shape of a bell, which can reduce a moat in an STI edge portion.
2. Description of the Prior Art
A shallow trench isolation (hereinafter, referred to as an STI) method has been used as an element isolation method until now.
An isolation layer formation method using this STI method will be described with reference to FIG. 1.
FIGS. 1a to 1e are cross-sectional views according to steps in a method of forming an isolation layer of a semiconductor device according to the prior art.
In the conventional method of forming an isolation layer as shown in FIG. 1a, a pad oxide layer 13 and a pad nitride layer 15 are laminated on a semiconductor substrate 11, and photoresist is coated on the pad nitride layer 15. Then, the lamination of the pad nitride layer 15, the pad oxide layer 13 and the photoresist is exposed to light and developed by photolithography, and is then selectively patterned to form a photosensitive film pattern 17 for a trench mask.
Next, as shown in FIG. 1b, the pad nitride layer 15 is etched using the photosensitive layer pattern 17 as a mask, and the pad oxide layer 13 and the substrate 11 are sequentially removed, so that a trench (not shown) for element isolation is formed. Next, in order to improve interfacial characteristic with an oxide layer, a linear oxide layer 19, which is a thermal oxide layer, is grown on a surface of the trench (not shown), so that an STI edge portion is rounded.
Next, as shown in FIG. 1c, a HDP oxide layer 21 is deposited on an upper surface of an entire structure including the trench (not shown) to fill the trench with the HDP oxide layer 21.
Next, as shown in FIG. 1d, the HDP oxide layer 21 is selectively removed by the CMP process, using the pad nitride layer 15 as an etching end point.
Next, as shown in FIG. 1e, the remaining pad nitride layer 15 is removed by a wet etching to form a trench isolation layer 21a, and a well formation and a threshold voltage ion implantation are performed, so that a gate oxide layer (not shown) is grown. Herein, in some cases, before ion implantation for a well formation after the pad nitride layer is removed, an oxide layer may be grown as a buffer layer for ion implantation.
Further, a field oxide layer is etched by cleaning solution through such a series of steps as described above. Herein, the field oxide layer of the STI edge portion is recessed downward. The shape of the recessed portion is called a moat.
When a moat occurs, silicon in the STI edge (i.e. silicon in an edge of an active area) is exposed, and the exposed portion may be thinned during growth of a gate oxide layer. Further, a gate electrode is formed to the moat portion, and therefore a voltage may be concentrated on the edge portion.
These phenomena cause a threshold voltage of a transistor to change, and therefore the transistor may operate at a lower voltage than a desired threshold voltage.
In order to solve theses problems, a front edge of the nitride layer, which is used as a mask for forming an STI pattern, may be retreated to an active area by means of phosphoric acid solution.
However, since this method uses the phosphoric acid more than 140°, it is difficult to maintain constant etch rate. Further, since a great deal of phosphoric acid is used, it is not preferable from an environmental standpoint.
Furthermore, since the silicon is exposed to a high temperature phosphoric acid solution, the silicon wafer may be damaged.